1. Technical Field
The embodiments described herein relate to a phase-change memory device, and more particularly to a phase-change memory device capable of reducing driving current while minimizing a size of a contact hole used for forming a PN diode in the phase-change memory device that employs the PN diode.
2. Related Art
It will be understood that Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and a flash memory are extensively used in a variety of devices. It will also be understood that a DRAM can be fabricated at a relatively low cost and represents a random access function, but it is a volatile memory. A SRAM used for a cache memory represents a random access function and a higher operational speed, but it is also a volatile memory and has a large size, resulting in high fabrication cost. A flash memory, on the other hand, is a nonvolatile memory and has advantages in terms of the fabrication cost and power consumption, but provides a lower operational speed.
A Phase-change Random Access Memory (PRAM) has been suggested to overcome the problems occurring in the above memory devices.
A PRAM is a memory device which records and reads out information by using a phase-change material that provides high resistance in an amorphous state and low resistance in a crystalline state. A conventional PRAM generally provides higher operational speed and a higher degree of integration as compared with a flash memory. Recently, in order to improve the degree of integration for PRAM, a cell in a conventional PRAM device can be formed using a diode structure.
FIG. 1 is a schematic sectional view showing a conventional PRAM device that uses such a cell. As shown in FIG. 1, an isolation layer 12 is formed on a semiconductor substrate 10 to define a core region and a cell region. Ions are implanted into the cell region, thereby forming a line type junction area 14.
Then, a gate stack 16 is formed in the core region and an interlayer dielectric layer 24 is formed on the entire structure including the core region and the cell region. Then, a predetermined portion of the interlayer dielectric layer 24 formed in the cell region is removed to form a contact hole 26 for forming a PN diode.
The gate stack 16 is prepared as a polycide structure. For instance, the gate stack 16 may consist of a hard mask nitride layer (HM Nit), metal silicide (for example, WSix) and a polysilicon layer. In addition, spacers 18 are formed at both sidewalls of the gate stack 16. Further, an oxide layer 20 and a nitride layer 22 are sequentially formed on the entire structure as a diffusion barrier. In general, the interlayer dielectric layer 24 is an oxide layer.
After forming the contact hole 26, a PN diode (not shown) is formed in the contact hole 26 through a selective epitaxial growth process.
In the above PRAM manufacturing process, the contact hole 26 must have a micro size to realize high integration of a device. However, there is a problem in that the bottom critical dimension D2 of the interlayer dielectric layer 24 has become smaller than the top critical dimension D1 of the interlayer dielectric layer 24 after the contact hole 26 has been formed through the mask and etching processes. That is, the interlayer dielectric layer 24 formed in the junction area 14 has a relatively large thickness of a few thousand Å, and an amount of etching gas has become reduced as it reaches the bottom of the interlayer dielectric layer 24. In addition, the oxide layer used as the interlayer dielectric layer 24 has etching selectivity similar to that of the oxide layer 20 formed on the junction area 14, so that the etching rate may be lowered at the bottom of the contact hole. As a result, the bottom critical dimension of a etching target layer is reduced by 80% as compared with the top critical dimension thereof.
For this reason, a contact area between the PN diode and the semiconductor substrate 10 may be reduced, causing the resistance to increase. As a result, the operational current is reduced, requiring a large driving current. In addition, as conventional semiconductor devices have become more highly integrated, the gap between PN diodes is reduced and resistance is increased at the bottom of the PN diode. In this case, a conventional semiconductor device may be subject to malfunction due to interference between adjacent diodes.